Given all the recent exposure from ourÂ Infineon research, we have had numerous requests regardingÂ the ST mesh architecture and how Infineon’s design compares to the ST implementation.Â
We tookÂ a few pictures of an area of each device with an electron microscope to give you a better idea.Â Both devices are a 4 metalÂ ~140 nanometer process.Â Rather than have us tell you who we think is stronger (it’s pretty obvious), we’d like to see your comments on what you the readers think!Â
In the picture above, the left side is the standard Infineon mesh with the standard ST mesh on the right.Â Â Both images were taken at 3,500 magnification.Â
The Infineon mesh consists of 5 zones with 4 circuits per zone.Â This means the surface of the die is being covered by 20 different electrical circuits.
The ST mesh consists of a single wire routed zig-zag across the die.Â It usually begins next to the VDD pad and ends at the opposite corner of the die.Â The other wires are simply GND aka ground fingers.Â On recent designs, we have caught ST using a few of the grounds to tie gates low (noise isolation of extra, unused logic we believe).Â
Zooming in at 15,000 magnification, the details of each mesh really begin to show.Â Where at lower resolutions, the Infineon mesh looked dark and solid but as you can see, it is not.
In the Infineon scheme above, each colored wire is the same signal (4 of them per zone).Â Each color will be randomly spaced per chip design and is connected at either the top or bottom of the die via Metal 3 inter-connects.
The ST simply has the single conductor labeled in red.Â All green are the fingers of ground which can be usually cutÂ away (removed)Â without penalty.Â Â The latest ST K7xxx devices have a signal present that appears analog.Â A closer look and a few minutes of testing proved it to simply need to be held high (logic ’1′) at the sampling side of the line.Â Interesting how ST tried to obscure the signal.
Infineon does not permanently penalize you if the mesh is not properly repaired and the device is powered up.Â
ST will permanently penalize you with a bulk-erase of the non-volatile memory (NVM) areas if the sense line (red) is ever a logic low (’0′) with power applied (irrelevant of reset/clock condition).
You tell us your opinion what you think security wise.Â Â Make sure you study the images closely beause there are other things we didn’t mention such as line spacing, etc. between the two designs which should be considered.