As you have a FIB / wirebonder, it’s probably quite easy for you to fix the Infineon mesh, if there are no connections from the middle of the mesh in down into the chip.
With a little help from the FIB / wirebonder you can simply bridge all green, blue, violet and yellow lines at the edge of the chip and then chemically dissolve / plasma etch the lines in the middle of the chip and then micro probe it.

The ST mesh looks meaner, but not impossible, especially if there are several chips available for analysis, and you can so you can which points of the red line are connected have connections into the chip and which are irrelevant. Then it should be possible to wirebond the interesting lines to Vcc.

BTW, is it possible to look through the protection mesh with high acceleration voltage? If the wires are made of aluminum (low atom number, high penetration depth) and the isolation made of SiO2 (also low atom number), then the electron beam with say 30keV (as in the picture) could perhaps have enough penetration depth to reach the layer below?!

If it does so, you could probably be able to have a limited vision through the top layer by using a backscatter / EDX detector, as the backscattered electrons / X-Rays have more energy and thus a limited ability to reach the detector through a few 100 nm of material.

But I know that it’s hard to distinguish between Al, Si and SiO2 in a Backscatter-SEM picture (little material contrast, because atom number are similar), so it might be be hard/impossible to get a good picture.

Secondary electrons are only able to penetrate a few nm of material, so SEs created inside the sample don’t reach the detector. Because of that you get sharper pictures by using a SE detector.

‘Infineon does not permanently penalize you if the mesh is not properly repaired and the device is powered up.’

I think it is the reason that the OS in the chip haven’t set the correlative SFR which is implemented to control the mesh operation.

Is there the OS inside the chip?

The ST top metal I’m guessing has a pitch of about 1.4 microns (or it’s a multiple of something for manufacturing). The mesh pattern seems like it’s protecting the chip from fat-fingering a probe or a some accidental shorting. It looks easier, although I sure wouldn’t call it easy.

I sure would hate to deal with all the extra wiring capacitance in the Infineon… just three layers of metal to work with, and all having high capacitance.

What happens when the Infineon chip starts up with a bad mesh? Does it act like a dead chip, or just allow a debug mode to confirm the chip is dead?

that being said, it’s probably a good idea to implement a verification step by means of signal delay / resistance measurements on a grid with MUX’d/DEMUX’d wires.